Field of the Invention
The present invention relates to an image processing technique of recording, in a recording apparatus, an image obtained by imaging, and performing display processing on a display device.
Description of the Related Art
In recent years, in an image processing apparatus having an imaging function such as a digital camera, processing data at a higher speed becomes more important along with an increase in processing data amount caused by a higher resolution of an image, an increase in the number of still image frames in continuous shooting, and improvement of moving image frame rates. On the other hand, however, processing a large amount of image data at a high speed increases the power consumption of an image processing apparatus, and thus increasing the data processing speed while reducing the power consumption is a big issue. Since a digital camera or a portable terminal having the imaging function is operated by a battery, there is demand for the number of recordable images to be increased while reducing the power consumption. To satisfy this requirement, it is especially important to suppress the power consumption as low as possible at the time of displaying a captured image on a monitor before recording the image.
There are conventionally known various techniques of attempting to increase the data processing speed while reducing the power consumption. Japanese Patent Laid-Open No. 2003-99149 describes a technique of attempting to increase the data processing speed while reducing the power consumption by stopping supply of a clock to a data-transfer controlling unit while standing by for permission of memory access. Furthermore, Japanese Patent Laid-Open No. 2006-236059 describes a technique of attempting to increase the data processing speed while reducing the power consumption by setting the minimum clock frequency corresponding to the number of clocks necessary for data transfer.
The above-described conventional techniques, however, are effective to optimize the number of clocks and the clock frequency but do not consider optimization of power supply, and need to continuously supply power to each data processing circuit during data transfer. This is because if power supply is stopped for each data transfer operation, the data processing speed largely decreases, since a power-up sequence requires several hundred μsec or longer for a general data transfer interval of several tens of nsecs to several μsec of a data processing apparatus. Also, if power supply to each data processing circuit is stopped, setting value information set by a CPU or the like in the data processing circuit is also lost. Therefore, if power supply is stopped for each data transfer operation, a reset time is required every time, thereby largely decreasing the data processing speed. In addition, a data transfer control sequence is complicated. In the above-described conventional techniques, a clock control arrangement is also complicated.